The role is part of the hardware design team in the Secure Mobile Transactions business within the client place. This team is tasked with delivering high quality solutions for mobile transactions (Secure Elements, NFC) to demanding mobile customers. A commitment to on-time delivery and strong focus on design quality is the foundation of all we do. The team is involved in all aspects of the design from specification to tapeout, validation, ramp to production and customer support.
Responsible for complete functional verification at block and SOC level of I2C , SPI, and UART
Interface to software, architecture, design teams, end user to understand functionality and application.
Define the verification and validation strategy for the design as a function of its architecture, the expected use cases, the technology the limitations of the tools and the schedule constraints.
Develop, debug, modify the test environment and test cases for different platforms (RTL, Emulation, FPGA, silicon).
Code testcases in an appropriate language and debug these test cases on the design models (RTL, Power aware RTL, Gates, Power aware gates, FPGA, Emulation platform) and on silicon.
Work with design and software teams to debug and correct issues or identify work-arounds. Add additional testcases to verify corrections or workarounds.
Determine the quality of the verification and validation by defining coverage goals and methods for measuring these goals. Enhance the testcases until the goals are met.
Perform pre-certification tests as required for standard interfaces
Interface to validation and product engineering teams for silicon correlation and debug.
Deep understanding of Metric driven verification, functional and code coverage.
Understanding of directed and constrained random methodologies.
Experience in Testbench design with standard verification frameworks like UVM/OVM.
Proficient in the languages used for testcase development (C, Verilog, System Verilog … )
Knowledge and experience of formal verification methodologies and assertions
Understanding of the architecture, elements and functionality of SOCs, including CPUs, DMA, MMU, PLLS, memory and peripheral interfaces.
Experience in verification of SOCs with significant analog content is a bonus.
Knowledge of product and IC/IP design processes.
Understanding of software development process for embedded CPUs and experience in developing and debugging software.
Expertise in the use of EDA tools for the development, simulation and debug of functional tests (RTL simulators, C compilers, debuggers )
Experience with debug on designs pre and post-silicon, in simulation and on the bench.
Thanks & Regards,
InspiriSYS Solutions Limited (Formerly Accel Frontline Ltd.)
Email: [email protected]